As a semiconductor substrate for a high-performance device, a bonded substrate obtained by bonding a bond wafer to a base wafer and then reducing a film thickness of the bond wafer is used. As one of such bonded substrates, an SOI substrate formed of silicon is known.
As a method for manufacturing an SOI substrate, the following bonding method is known, for example. That is, two mirror-polished silicon wafers (a bond wafer and a base wafer) are prepared, and an oxide film is formed on at least one of the wafers. Further, these wafers are bonded to each other through the oxide film, and then a heat treatment is performed to increase bonding strength. Thereafter, a film thickness of the bond wafer is reduced to obtain an SOI substrate on which an SOI (Silicon on Insulator) layer is formed. As a method for reducing this film thickness, the film thickness of the bond wafer is reduced to some extent based on grinding or etching, and then a surface thereof is subjected to mechanochemical polishing, thereby finishing the wafer with a desired SOI layer thickness.
Although the SOI wafer manufactured by this method has a merit that crystallinity of the SOI layer or reliability of the oxide film is as high as that of a regular semiconductor wafer, this manufacturing method has a drawback that there is a limit in uniformity of a film thickness of the SOI layer and radial uniformity of at most approximately 0.3 μm can be obtained with respect to a target film thickness even though a highly accurate machining technique is adopted. Furthermore, only one SOI wafer can be obtained from two semiconductor wafers, resulting in a problem of an increase in cost.
Japanese Patent Application Laid-open No. H5-211128 has recently proposed a method for bonding an ion implanted wafer to another wafer and then performing a heat treatment to carry out delamination at an ion implanted layer, i.e., a so-called an ion implantation delamination method as a new method for manufacturing an SOI wafer. This method is a technology of forming an oxide film on at least one of two silicon wafers, implanting a hydrogen ion or a rare gas ion from main surface of a bond wafer, forming a micro bubble layer (an ion implanted layer) in the wafer, then closely contacting the ion implanted surface with a base wafer through the oxide film, performing a heat treatment (a delamination heat treatment) to delaminate the bond wafer in a thin film with the micro bubble layer being used as a cleavage plane, and further performing a heat treatment (a bonding heat treatment) to firmly bond the wafers in some cases, thereby obtaining an SOI wafer.
According to this method, an SOI wafer having film thickness uniformity of ±0.01 μm can be relatively easily obtained.
Meanwhile, an SOI wafer in which an SOI layer has a relatively large film thickness of several μm to several-ten μm is very useful for a bipolar device or a power device, and its future development is greatly expected. When manufacturing an SOI wafer having such a relatively large film thickness in a conventional technology, a bond wafer is first bonded to a base wafer through an oxide film based on the bonding method, a bonding heat treatment is performed at approximately 1100° C., and then grinding and polishing processes are carried out to manufacture the SOI wafer having a desired film thickness. However, at this case, since an unbonded portion is produced at a wafer peripheral portion, an edge machining process for removing the unbonded portion must be performed before polishing, thereby resulting in a problem of a complicated process or an increase in cost. Moreover, the polishing process alone cannot improve uniformity of the film thickness of the SOI layer as explained above, and a vapor phase etching process called a PACE (Plasma Assisted Chemical Etching) method disclosed in Japanese Patent Application Laid-open No. H5-160074 is used to uniform the film thickness and haze and others are removed based on mirror polishing. However, there is a drawback that performing polishing after vapor phase etching in this manner degrades uniformity of the film thickness of the SOI layer to introduce a latent scratch or a damaged layer and crystallinity is apt to be degraded, and a cost is still high.
On the other hand, the ion implantation delamination method has a great merit in terms of productivity or a cost since the edge machining process that is necessary in the wafer bonding method is not required. However, since an acceleration voltage of an ion implantation apparatus determines an implantation depth of an ion and this further determines a film thickness of the SOI layer, an acceleration voltage of approximately 20 keV is a limit in a large-current ion implantation apparatus that is usually utilized as a mass-produced apparatus because of a restriction in the apparatus, and hence only an SOI layer having a film thickness of at most approximately 2 μm can be fabricated. Therefore, in order to form an SOI layer having a larger film thickness based on the ion implantation delamination method, although the large-current ion implantation apparatus that can obtain a higher acceleration voltage is required, obtaining a large current is difficult in the apparatus that can obtain a high acceleration voltage exceeding 200 keV, a time to obtain a predetermined implantation amount is required and this leads to an increase in cost, and hence a practical application on a mass production level is not realized. Additionally, the same problem as that of the PACE method is present in a point that a process, e.g., polishing is required to improve surface roughness of an SOI surface after delamination.
To solve the above-explained problem, Japanese Patent No. 3358550 discloses a method for manufacturing an SOI wafer by forming an oxide film on at least one of a bond wafer and a base wafer, implanting a hydrogen ion or a rare gas ion from a main surface of the bond wafer to form an ion implanted layer, then closely contacting the ion implanted surface with the base wafer through the oxide film, applying a heat treatment, separating the bond wafer in a thin film while using the ion implanted layer as a cleavage plane (a delamination surface) to fabricate an SOI wafer (an SOI wafer serving as a substrate) having an SOI layer, and then growing an epitaxial layer on the SOI layer to form an SOI layer having a relatively large film thickness.
However, when performing the epitaxial growth at a high temperature by using a lamp heating type epitaxial growth apparatus on the SOI layer of the SOI wafer serving as a substrate based on the above-explained method, there is a problem that slip dislocation and others are apt to occur on the wafer to degrade a quality of the SOI wafer, and this must be improved.